The present invention relates generally to integrated circuits, and more particularly, to a well-biasing circuit for an integrated circuit.
Integrated circuits (ICs) include transistors such as complementary metal-oxide semiconductor (CMOS) transistors that are used to implement logic circuitry. ICs often operate in different power modes including RUN, STANDBY and STOP modes for effective power management. When an IC enters STANDBY or STOP modes (i.e., a low power mode), leakage currents are generated. The leakage currents are a major source of power consumption, especially when the IC includes a large number (in the order of millions) of transistors.
One way of reducing leakage currents is to increase the threshold voltage of the transistors. For CMOS transistors, biasing of the n-well and p-well regions increases the threshold voltage, which reduces the leakage current. Providing a low voltage to the p-well region and a high voltage to the n-well region with respect to a source potential of a CMOS transistor increases the threshold voltage of the CMOS transistor and results in reduced leakage current. When an IC operates in the RUN mode, the n-well region is biased by a core supply voltage of the IC and the p-well region is biased by a ground voltage. To increase the threshold voltage during the STOP and STANDBY modes, the n-well region may be biased with a voltage that is higher than the core supply voltage and the p-well region may be biased with a voltage that is lower than the ground voltage.
Existing ICs use well-biasing circuits to generate and provide different well-bias voltages (to the n-well/p-well regions) during different operating modes of the ICs. The well-biasing circuits include a switch (e.g., a MOS switch) connected between the core power supply/ground and the well-bias contact. When the IC is in the STOP and STANDBY modes, the switch must open completely to disconnect the well-bias contact from the core power supply/ground and reduce the possibility of leakage currents. The gate control voltage of the MOS switch must be maintained greater than or equal to the well-bias voltage to ensure complete opening of the switch. A high-voltage MOS switch is required to maintain the gate control voltage higher than the well-bias voltage. However, this high-voltage MOS switch consumes a lot of power and occupies a large area. Alternatively, a low-voltage MOS switch can be used to keep the gate control voltage equal to the well-bias voltage. However, the gate control voltage of the low-voltage MOS switches used by existing well-biasing circuits fails to track the well-bias voltage. As a result, the low-voltage MOS switch starts conducting leakage current and makes the well-biasing circuit unreliable.
It would be advantageous to have a well-biasing circuit for an IC that reduces the leakage currents in the IC, that is reliable and that overcomes the above-mentioned limitations of existing well-biasing circuits.